1. Field of the Invention
The present invention relates to a pipeline circuit adopted for a CPU or a microprocessor in a computer system. Particularly, the present invention relates to a pipeline circuit which computes the effective branch destination address of a conditional branch instruction before or in parallel with the execution of the conditional branch instruction, judges according to a result of the execution of an instruction just before the conditional branch instruction whether or not a branch condition of the conditional branch instruction is met, and, if the branch condition is met, executes the conditional branch instruction while prefetching and decoding an instruction located at the branch destination address.
2. Description of the Prior Art
To improve the processing speed of a microprocessor or a CPU in a computer system, various pipeline circuits have been developed.
Generally, the pipeline circuit decomposes a series of processes starting from an instruction fetching operation to an instruction executing operation into a plurality of steps, and processes the steps in separate circuit stages where the instruction is transferred from the first stage toward the last stage while being processed. According to the pipeline circuit, instructions are not processed one by one but processed in parallel with each other in the respective circuit stages.
FIG. 1 is a view showing an example of a pipeline circuit adopted for a CPU according to a prior art.
In the figure, a pipeline circuit 1 comprises an instruction fetching unit (IFU) 2, an instruction decoding unit (IDU) 3 and an instruction executing unit (EXU) 4.
The IFU 2 fetches an instruction from a memory 5, stores the same in an instruction buffer (not shown), and reads out an instruction stored in the instruction buffer to send the same to the IDU 3. The IDU 3 decodes the instruction supplied from the IFU 2 and sends a decoded instruction to the EXU 4. The EXU 4 executes the decoded instruction sent from the IDU 3.
FIG. 2 shows the processes carried out in the pipeline circuit 1 in handling an instruction A1 which is not a conditional branch instruction and a conditional branch instruction Bcc following the instruction A1.
For the sake of explanation,, an instruction fetching operation in the IFU 2 and a decoding operation in the IDU 3 are supposed to be carried out each within one clock cycle, and an effective destination address of the conditional branch instruction Bcc is supposed to be computed in the EXU 4.
The instruction A1 is fetched in a clock cycle T1, decoded in a clock cycle T2 and executed in clock cycles T3 to T5. In parallel with the execution of the instruction A1, the next conditional branch instruction Bcc is supplied to the IDU 3 in the clock cycle T2, decoded in the clock cycle T3 and executed in clock cycles T6 and T7.
The execution of the instruction Bcc includes judging (checking a flag) whether or not a branch condition of the instruction Bcc is met, computing a branch destination address of the instruction Bcc if the branch condition is met, etc.
If the branch condition is met, an instruction C1 located at the branch destination address is fetched in a clock cycle T8 and decoded and executed in clock cycles starting from T9.
As described in the above, when a conditional branch instruction is supplied to the pipeline circuit and if a branch condition of the branch instruction is met, prefetched instructions are abandoned, and an instruction located at a branch destination address starts to be fetched. Therefore, execution stage of the pipeline circuit waits for the completion of fetching and decoding the instruction located at the branch destination address so that the processing speed of a CPU including the pipeline circuit may be slowed.
To solve the problem of branch in the pipeline circuit, various pipeline circuits have been developed. However, they encountered other problems, in improving the processing time of conditional branching operation, e.g., increased amounts of hardware and complicated controls.